Photonic Layout & Tape-Out Engineer
HyCom Core · Espoo
Onsiteentry💰 3,400–4,150 EUREngineering · TechnologyPosted 02/11/2026, 02:00
Skills
photonicselectrical_engineeringmicroelectronicsPythonGitlayout_designphysical_verificationdocumentation
Job Description
Company Description
HyCom Core focuses on delivering high-performance, scalable connectivity solutions that address the growing demands of modern computing infrastructure. The company offers an opportunity to work with cutting-edge photonic technologies that are shaping the future of data movement and hardware architectures.
Role Description
The Photonic Layout & Tape-Out Engineer is an on-site role based in Espoo. In this position, the engineer creates and optimizes photonic and associated electronic layouts, ensuring alignment with circuit specifications and performance targets. Day-to-day responsibilities include collaborating with circuit designers, performing physical verification, preparing designs for tape-out, and resolving layout-related issues across the design flow. The engineer works closely with cross-functional teams to validate design manufacturability, implement design rule checks, and support continuous improvement of layout methodologies and tools.
Qualifications
You do not need to match every item. We are especially interested in students who are curious, careful and motivated to learn.
Currently pursuing, or recently completing, a Master’s degree in photonics, electrical engineering, microelectronics, physics, software engineering or a related field.
Working knowledge of Python and interest in writing maintainable, well-documented code.
Familiarity with Git or another version-control workflow.
Structured problem-solving skills, attention to detail and clear communication.
Interest in integrated photonics, semiconductor layout, design automation or fabrication workflows.
Helpful, but not required
Experience with PIC or semiconductor physical layout, GDSII or tape-out workflows.
Exposure to foundry PDKs, DRC rule decks, layer mapping or layout verification.
Experience with KLayout, gdsfactory or comparable layout tools.
Understanding of optical waveguide routing, characterization structures or packaging-related layout constraints.
Familiarity with integrated photonics and photonic and/or electrical layouts.